Ex-Nokia Executive: Windows Phone Does Not Allow Nokia to Realize Its Potential.

Although many criticize Nokia's Symbian operating system today, recent quarter's €3 billion revenue drop and €1.3 billion loss clearly point to the fact that the transition to Windows Phone was a mistake. A former executive from Nokia claims that the current chief exec of the company lacks vision and Nokia should have stuck to its own platforms, e.g., MeeGo to realize its potential.
"Stephen Elop has not delivered a roadmap. He has been there for two to three years and there's really no roadmap. There's no overarching vision for this company. [...] Elop is operating like a chief financial officer - CFOs are very practical, always looking at costs, always internally focused. I do not think he is really projecting anything forward or sitting around with his team imaging what the future looks like. I think it is 's**t how do I get rid of a third of this overhead in R&D?'," said Lee Williams, a former senior vice president of Nokia in charge of Symbian, in an interview with Cnet UK web-site.
While Mr. Williams admits that Nokia was executing poorly in the late '00s, it was on the fundamentally right direction: it had very popular Symbian platform (which managed to outsell Apple iOS even in Q1 2011) and it was developing MeeGo platform that could rival both Apple iOS and Google Android on flagship devices.

But Stephen Elop, the current CEO of Nokia, decided to pre-announce transition from Symbian to Windows Phone, which dropped sales of Symbian-based devices immediately, and cancel all the works on the MeeGo operating system. While two or three Windows Phone-based models might make sense for Nokia, putting all eggs into the basket of one OS that had failed to become popular, was a rather controversial decision. In fact, with about two million life-to-date shipments of all Nokia Lumia WP 7.5-based smartphones, it is clear that the decision was more than just controversial.
"When I was at Nokia and we shipped a Symbian product and it was bad, in its worst incarnation we knew that if we just flipped the switch, we could move 2.5 to 3 million units overnight, no matter how bad the product. That was Nokia. That was Nokia's brand, we knew we could count on that. Now look at it: they flipped the switch and oh, 200 thousand [Windows Phone] units out of the gate. Huh? Only selling in the US, under AT&T's moniker. If you cannot flip the switch like that, Nokia's dead and devalued," claims Mr. Williams.

One operating system does not serve well on tens or hundreds of devices. Therefore, there is no right decision when choosing between Android, MeeGo, Symbian or Windows Phone as a single platform. What matters are two things: great fit of an OS for a particular product and ability to develop unique devices with exclusive differentiators.
Over the years, Nokia has developed many exceptional innovations that could become major unique features for its phones. However, with a third-party platform, such as Google Android or Microsoft Windows Phone, this cannot be done. For example great Nokia's photo capabilities cannot be realized under Windows Phone.
"The 'in house' software and expertise Nokia had and in some cases still have, created differentiators, and features that needed better market presence, and they needed to realise the benefits of a true ecosystem of software and service providers. Android is not and I do not believe will be the answer to this situation for Nokia. [...] Now they have a Windows Phone product, and the differentiators are nonexistent, the battery life is orders of magnitude behind their other products, and the best imaging or camera features are not able to be fully realized leveraging the Windows Phone code," stressed the former Nokia executive.
All-in-all, Mr. Elop will have from six to twelve months to return Nokia onto the course of own software, according to Mr. Lee. However, the company might have to get rid of certain divisions to stay alive...
"I'm confident they will be able to course correct and that they have the kind of assets and talent left to be able to do something here. I don't see them going out in a firesale. I think what will happen is they'll sell off some divisions, and/or will simply gut leadership quickly and change course a little bit, back in the direction of where they were going," concluded Lee Williams.

Intel Wants a Significant Chunk of Cell Phone Market Share.

After attempts to make it into mass smartphones that have lasted for ten years, Intel is finally inside several devices that are about to hit the market. While only time will tell whether the first breed of Intel Atom-based smartphones will be a success, Intel itself claims that it entered the market of mobile phones very seriously and for the win.
"Intel does not go into markets to be a small player. It is a billion-unit market, so there is a huge opportunity for us," said Stacy Smith, chief financial officer of Intel, in an interview with Bloomberg news-agency.
Starting from the Q2 2012 several companies, including Lava (which is already selling its devices), Orange and ZTE, in addition to Motorola Mobility and Lenovo, plan to release their x86 smartphones based on Intel Atom Z2460 platform in different parts of the world. The first three companies intend to use Intel's reference design and add their proprietary features to them in a bid to differentiate themselves from others, whereas Lenovo and Motorola/Google have their own developments based on Intel Atom system-on-chip with their own set of capabilities.
“As of a week ago, we had zero share. As of this week, it is zero-point-something, because the first phones are selling,” said Mr. Smith.
At present, Intel only sells application processors for smartphones, which means that its clients have to use third-party baseband processors to enable network connection. In the future, Intel will integrate its baseband capabilities into its system-on-chips for smartphones, which will not only allow it to target mainstream smartphones, but will put it directly against powerful ARM partners, such as Qualcomm, Texas Instruments and Nvidia (which is supposed to release its WWAN-enabled Tegra in early 2013). Will Intel's chips be competitive? Only time will tell.
Intel smartphone reference design is based on Atom Z2460 system-on-chip (Atom core at 1.60GHz, PowerVR-based graphics core with OpenGL ES 2.0, OpenGL 2.1, OpenVG 1.1 support clocked at 400MHz with hardware accelerated high-definition 1080p video playback, 32-bit LPDDR2 memory controller and so on) supporting HSPA+ with the Intel XMM 6260 communication processor. The reference design smartphones have 4.03" screens, 8MP cameras and use Google Android 4.0 operating system.

AMD, Globalfoundries, Others Set to Use Fully-Depleted SOI with 14nm, 20nm Chips.

Soitec, a leading designer of materials for semiconductors, has announced its fully depleted (FD) product roadmap comprising two products designed for both planar and three-dimensional (FinFET) approaches to building transistors. Industry checks by X-bit show that AMD, Globalfoundries and some other companies are interested in FDSOI for 20nm chips.
"Our fully depleted product roadmap addresses the critical needs of the semiconductor industry and solves key challenges facing manufacturers today. Whichever path chip vendors choose to follow – planar or FinFET – Soitec provides solutions that address cost, performance, power-efficiency and time-to-market issues. FD-2D enables immediate and significant performance leaps, while FD-3D makes FinFET a reality for the entire industry at accelerated schedules and reduced risk," said Paul Boudre, chief operating officer of Soitec.
Based on industry checks, X-bit labs believes that Globalfoundries and other partners will use fully-depleted SOI with its 20nm processes and more advanced technologies for making chips, including those designed by Advanced Micro Devices.

Fully-depleted wafers from Soitec, pre-integrate critical characteristics of the transistor within the wafer structure itself. Soitec’s FD wafers offer an early, low-risk migration at the 28nm node down to 10nm and beyond, lowering costs and enabling significant advances in the performance and power efficiency of mobile devices such as smartphones and tablets.
Soitec’s FD-2D product line enables a unique planar approach to fully depleted silicon technology as early as the 28nm node, in which chipmakers can continue to leverage their existing designs and process technologies. FD-2D also enables immediate gains in performance and energy efficiency for mobile and consumer multimedia chips.
The company’s FD-3D product line facilitates the introduction of three-dimensional (FinFET) architectures with reduced time and investment, and drives substantial simplifications in the transistor fabrication process, targeting nodes below 20nm.
Soitec’s proprietary Smart Cut layer transfer technology is said to generate thin layers with high quality and uniformity, bringing the ability to tune starting wafers to successive technology nodes and delivering key advantages as chip manufacturers pursue the best performance, efficiency and manufacturability results.

Globalfoundries' Fab 8 to Enable 3D Stacking of Chips.

Globalfoundries said Thursday that it had begun to install a special set of production tools to create through-silicon vias (TSVs) in semiconductor wafers processed on the company's leading-edge 20nm technology platform at Fab 8. The TSV capabilities will allow customers to stack multiple chips on top of each other, providing another avenue for delivering the demanding requirements of future electronic devices.
TSVs (vertical holes etched in silicon and filled with copper) enable communication between vertically stacked integrated circuits. For example, the technology could allow circuit designers to place stacks of memory chips on top of an application processor, which can dramatically increase memory bandwidth and reduce power consumption, a key challenge for designers of the next generation of mobile devices such as smartphones and tablets.
At leading-edge nodes, the adoption of 3D stacking of integrated circuits is increasingly being viewed as an alternative to traditional technology node scaling at the transistor level. However, as new packaging technologies are introduced, the complexity of chip-package interaction is going up significantly and it is increasingly difficult for foundries and their partners to be able to deliver end-to-end solutions that meet the requirements of the broad range of leading-edge designs.

"To help address forthcoming challenges on new silicon nodes, we are engaging early with partners to jointly develop packaging solutions that will enable the next wave of innovation in the industry. Our approach is broad and collaborative, giving customers maximum choice and flexibility, while delivering cost savings, faster time-to-volume, and a reduction in the technical risk associated with developing new technologies. With the installation of TSV capabilities for 20nm technology in Fab 8, we are adding an important capability that will be supplemented by our joint development and manufacturing partnerships with companies across the semiconductor ecosystem, from design to assembly and test," said Gregg Bartlett, chief technology officer of Globalfoundries.
Globalfoundries' new Fab 8 campus stands as one of the most technologically advanced wafer fabs in the world and the largest leading-edge semiconductor foundry in the United States. The site is focused on leading-edge manufacturing at 32/28nm and below, with 20nm technology development well underway. The first full-flow silicon with TSVs is expected to start running at Fab 8 in Q3 2012.

WD Continues to Rapidly Restore HDD Unit Shipments with Help of Hitachi GST.

Western Digital on Thursday said that it had managed to significantly restore production capacities after devastating flooding in Thailand in October, 2011. In the Q3 of the company's FY2012 (ended on March 30, 2012) WD itself and its Hitachi GST subsidiary (which officially became a part of WD in early March and thus only shipped for WD for 3.5 weeks) sold 44.2 million hard drives.
WD reported revenue of $3.0 billion (including $614 million for HGST), hard-drive unit shipments of 44.2 million with average selling price of $68 and net income of $483 million, or $1.96 per share, on a GAAP basis for its third fiscal quarter ended March 30, 2012. In the previous quarter (calendar Q4 2011) Western Digital shipped 28.5 million of hard drives and reported revenue of $2.0 billion amid net income of $145 million. In the year-ago quarter, the company reported revenue of $2.3 billion, net income of $146 million and shipped 49.8 million hard drives.
"I am pleased to announce today that the recovery activities related to both WD operations and those of our supply chain partners impacted by the Thailand floods have reached a point where we now have the capability to adequately meet anticipated customer demand in the current quarter and beyond," said John Coyne, chief executive officer of Western Digital.
Rapid increase of shipments by whopping 55% from 28.5 million hard disk drives to 44.2 million drives in one quarter is a significant achievement, even keeping in mind that for 3.5 weeks of the quarter WD also sold Hitachi-branded hard drives. Hitachi also suffered from the flooding and therefore WD's management will have to work hard to restore HGST's manufacturing capacities as well. Nonetheless, it is clear that WD can is just about 11% behind its shipments in the same period last year and is likely to be on-track to restore all of its (and possibly HGST's) production facilities by late June.

"Our third quarter performance demonstrates the potential of the new Western Digital, with just three and a half weeks of HGST results combined with the standalone WD business. Competing in the marketplace with our separate WD and HGST subsidiaries, we now have the product portfolio, technology resources and the people to fully serve the needs of a significantly expanded customer base and to better address the tremendous growth opportunities in the storage industry in the years ahead," added Mr. Coyne.

Nvidia: Power Efficiency of Kepler - Result of Close Collaboration with TSMC.

It is not a secret that performance, cost and power efficiency of chips depend on actual design as well as on process technology. A good chip design and advanced process technology almost always result in a proper product. But to make the best chip, its design has to be tailored for process technology and vice versa. Apparently, this is exactly what Nvidia and TSMC have done to make Kepler architecture exceptionally power-efficient.
"Today, the primary constraint on processor performance is the power consumption budget. So our goal is always to develop solutions that deliver the highest performance within a fixed power budget. Having a more efficient process enabled us to add more processing cores, thus increasing performance. Put simply, greater efficiency equals greater performance and optimal performance per watt," said Joe Greco, senior vice president of the advanced technology group at Nvidia.
Kepler was in many ways an ambitious project because it introduced a new architecture at the same time as a new silicon process technology node. To maximize the efficiency of Kepler architecture, which Nvidia needed not only to sustain leading positions on the market of computer graphics, but also to continue its progress on the market of high-performance computing, Nvidia had tochange our silicon process development model with TSMC.
Back in the days Nvidia and Taiwan Semiconductor Manufacturing Company worked independently:  TSMC prepared the process technology, Nvidia worked on the design. For Kepler, Nvidia began working with TSMC three years before our product tape-out (when the processor design is complete and ready for manufacturing). Working in tandem, the two companies created a production qualification vehicle (PQV) to allow the TSMC process engineers and Nvidia design engineers to optimize the process before the product tape-out. Through repeated prototyping, the companies were able to optimize both the process and design, creating a more efficient Kepler design rather than simply a chip in a standard 28nm process.

This is not the first time when TSMC collaborates with its major customers to tailor process technology for their needs and also not the first  time when chip designs are optimized for a process technology still in development. As chips get more complex and manufacturing technologies get thinner, even closer collaboration between chip designers and contract makers of semiconductors will be needed to create great products.
TSMC’s 28nm high performance (HP) process, the foundry’s most advanced 28nm process which uses high-K metal gate (HKMG) technology and SiGe (Silicon Germanium) straining. HKMG is a process that uses a gate insulator film with a high dielectric constant which reduces power by reducing gate leakage compared to the previous generation SiON gate. SiGe straining is a chemical process to stretch the silicon atoms to improve the mobility or the effective frequency of the transistor. Both technical advances improve the performance per watt of the transistor translating to a more power efficient system.

^{TSMC’s 28nm HP process, seen under an electron microscope, is 30% smaller than 40nm and about 35% more energy efficient.}

"We are extremely proud of what we accomplished with Kepler. It combines Nvidia’s world-class GPU engineering with TSMC’s very best 28nm process. But while Kepler was a key milestone, it is one point in a continuum. We continue to improve on what we developed and continue our collaboration with TSMC. In fact, we recently received our first version of an enhanced PQV for 20nm from TSMC. That process will yield even greater efficiency for Nvidia’s next next-generation GPUs," said Mr. Greco.

Nvidia: Power Efficiency of Kepler - Result of Close Collaboration with TSMC.

t is not a secret that performance, cost and power efficiency of chips depend on actual design as well as on process technology. A good chip design and advanced process technology almost always result in a proper product. But to make the best chip, its design has to be tailored for process technology and vice versa. Apparently, this is exactly what Nvidia and TSMC have done to make Kepler architecture exceptionally power-efficient.
"Today, the primary constraint on processor performance is the power consumption budget. So our goal is always to develop solutions that deliver the highest performance within a fixed power budget. Having a more efficient process enabled us to add more processing cores, thus increasing performance. Put simply, greater efficiency equals greater performance and optimal performance per watt," said Joe Greco, senior vice president of the advanced technology group at Nvidia.
Kepler was in many ways an ambitious project because it introduced a new architecture at the same time as a new silicon process technology node. To maximize the efficiency of Kepler architecture, which Nvidia needed not only to sustain leading positions on the market of computer graphics, but also to continue its progress on the market of high-performance computing, Nvidia had tochange our silicon process development model with TSMC.
Back in the days Nvidia and Taiwan Semiconductor Manufacturing Company worked independently:  TSMC prepared the process technology, Nvidia worked on the design. For Kepler, Nvidia began working with TSMC three years before our product tape-out (when the processor design is complete and ready for manufacturing). Working in tandem, the two companies created a production qualification vehicle (PQV) to allow the TSMC process engineers and Nvidia design engineers to optimize the process before the product tape-out. Through repeated prototyping, the companies were able to optimize both the process and design, creating a more efficient Kepler design rather than simply a chip in a standard 28nm process.

This is not the first time when TSMC collaborates with its major customers to tailor process technology for their needs and also not the first  time when chip designs are optimized for a process technology still in development. As chips get more complex and manufacturing technologies get thinner, even closer collaboration between chip designers and contract makers of semiconductors will be needed to create great products.
TSMC’s 28nm high performance (HP) process, the foundry’s most advanced 28nm process which uses high-K metal gate (HKMG) technology and SiGe (Silicon Germanium) straining. HKMG is a process that uses a gate insulator film with a high dielectric constant which reduces power by reducing gate leakage compared to the previous generation SiON gate. SiGe straining is a chemical process to stretch the silicon atoms to improve the mobility or the effective frequency of the transistor. Both technical advances improve the performance per watt of the transistor translating to a more power efficient system.

^{TSMC’s 28nm HP process, seen under an electron microscope, is 30% smaller than 40nm and about 35% more energy efficient.}

"We are extremely proud of what we accomplished with Kepler. It combines Nvidia’s world-class GPU engineering with TSMC’s very best 28nm process. But while Kepler was a key milestone, it is one point in a continuum. We continue to improve on what we developed and continue our collaboration with TSMC. In fact, we recently received our first version of an enhanced PQV for 20nm from TSMC. That process will yield even greater efficiency for Nvidia’s next next-generation GPUs," said Mr. Greco.

Intel Aims to Rigorously Compete Against Nvidia, Qualcomm, TI, Others

After attempts to make it into mass smartphones that have lasted for ten years, Intel is finally inside several devices that are about to hit the market. While only time will tell whether the first breed of Intel Atom-based smartphones will be a success, Intel itself claims that it entered the market of mobile phones very seriously and for the win.
"Intel does not go into markets to be a small player. It is a billion-unit market, so there is a huge opportunity for us," said Stacy Smith, chief financial officer of Intel, in an interview with Bloomberg news-agency.
Starting from the Q2 2012 several companies, including Lava (which is already selling its devices), Orange and ZTE, in addition to Motorola Mobility and Lenovo, plan to release their x86 smartphones based on Intel Atom Z2460 platform in different parts of the world. The first three companies intend to use Intel's reference design and add their proprietary features to them in a bid to differentiate themselves from others, whereas Lenovo and Motorola/Google have their own developments based on Intel Atom system-on-chip with their own set of capabilities.
“As of a week ago, we had zero share. As of this week, it is zero-point-something, because the first phones are selling,” said Mr. Smith.
At present, Intel only sells application processors for smartphones, which means that its clients have to use third-party baseband processors to enable network connection. In the future, Intel will integrate its baseband capabilities into its system-on-chips for smartphones, which will not only allow it to target mainstream smartphones, but will put it directly against powerful ARM partners, such as Qualcomm, Texas Instruments and Nvidia (which is supposed to release its WWAN-enabled Tegra in early 2013). Will Intel's chips be competitive? Only time will tell.
Intel smartphone reference design is based on Atom Z2460 system-on-chip (Atom core at 1.60GHz, PowerVR-based graphics core with OpenGL ES 2.0, OpenGL 2.1, OpenVG 1.1 support clocked at 400MHz with hardware accelerated high-definition 1080p video playback, 32-bit LPDDR2 memory controller and so on) supporting HSPA+ with the Intel XMM 6260 communication processor. The reference design smartphones have 4.03" screens, 8MP cameras and use Google Android 4.0 operating system.

Apple is Ten Years Behind Microsoft with Security Technologies - Antivirus Developer.

As Apple Macintosh computers get more popular among end-users, more and more viruses and malware emerge for the platform, which has been known for its invulnerability, and more Mac personal computers get attacked. To make the matters worse, Eugene Kaspersky, the head of Kaspersky Lab, a leading PC security company, claims that Apple is significantly behind Microsoft when it comes to security.
"I think they are ten years behind Microsoft in terms of security. For many years I have been saying that from a security point of view there is no big difference between Mac and Windows. It has always been possible to develop Mac malware, but this one was a bit different. For example it was asking questions about being installed on the system and, using vulnerabilities, it was able to get to the user mode without any alarms," said Eugene Kaspersky, chief executive officer of Kaspersky Lab, in an interview with CBR web-site.
It has always been a matter of time before mass malware for Apple Macintosh platform would emerge. Recent record sales of Macs have just catalyzed designers of viruses to develop  malicious software for Apple computers. The problem is that Microsoft is ready to fight the problems all the time and release appropriate patches within hours after a problem transpires. Apple could not react instantly on the recent Flashback and Flashfake outbreaks.
"Apple is now entering the same world as Microsoft has been in for more than 10 years: updates, security patches and so on. We now expect to see more and more because cyber criminals learn from success and this was the first successful one," said Mr. Kaspersky.
Essentially, Apple will have to do what Microsoft did ten years ago. It will have to reconsider update policy, create rapid-response security teams and invest more into security of its Mac OS in general.
"They will understand very soon that they have the same problems Microsoft had ten or 12 years ago. They will have to make changes in terms of the cycle of updates and so on and will be forced to invest more into their security audits for the software. That is what Microsoft did in the past after so many incidents like Blaster and the more complicated worms that infected millions of computers in a short time. They had to do a lot of work to check the code to find mistakes and vulnerabilities. Now it's time for Apple [to do that]," concluded one of the world's top security experts.

Western Digital Confirms Development of Hybrid Hard Drives.

Western Digital on Thursday confirmed that it had started development of hybrid hard drive (HHD), which combines rotating magnetic media and NAND flash in a single storage solution. With the acquisition of Hitachi GST and its expertise with solid-state drives, it is likely that the HHD initiative at WD will speed up.
"We are continuing investments in strategic growth areas such as SSD, hybrid drives and the digital home," said John Coyne, chief executive officer of WD, during quarterly conference call with financial analysts.
Last year Western Digital said that it started to evaluate feasibility of hybrid drives as solid-state drives did not, in WD's opinion, provide the right value proposition for the client PC market. The destiny of the hybrid drive initiative at Western Digital has so far been unclear.

Apart from Samsung Electronics and Toshiba Corp., which are the world's largest makers of flash memory, neither of leading-edge makers of hard disk drives - Hitachi, Seagate and Western Digital - have unveiled broad lineups of solid-state drives for consumers. By contrast, various suppliers of branded memory modules have already launched large families of own-brand SSDs. Moreover, OCZ Technology, formerly known for memory modules, even managed to become a leading manufacturer of both client, server and enterprise solid-state storage solutions, posing a threat to hard disk drives.
So far, only Seagate Technology has released Momentus XT hybrid hard drive with 8GB of single-level cell (SLC) NAND flash memory and 750GB rotating media. Momentus XT uses Adaptive Memory technology to identify data usage patterns, and then move the most frequently retrieved information to solid state memory for faster access. Adaptive Memory effectively tailors hard drive performance to each user and the applications they use.
No details about forthcoming hybrid hard drive from Western Digital are available today.

AMD, Globalfoundries, Others Set to Use Fully-Depleted SOI with 14nm, 20nm Chips.

Soitec, a leading designer of materials for semiconductors, has announced its fully depleted (FD) product roadmap comprising two products designed for both planar and three-dimensional (FinFET) approaches to building transistors. Industry checks by X-bit show that AMD, Globalfoundries and some other companies are interested in FDSOI for 20nm chips.

"Our fully depleted product roadmap addresses the critical needs of the semiconductor industry and solves key challenges facing manufacturers today. Whichever path chip vendors choose to follow – planar or FinFET – Soitec provides solutions that address cost, performance, power-efficiency and time-to-market issues. FD-2D enables immediate and significant performance leaps, while FD-3D makes FinFET a reality for the entire industry at accelerated schedules and reduced risk," said Paul Boudre, chief operating officer of Soitec.

Based on industry checks, X-bit labs believes that Globalfoundries and other partners will use fully-depleted SOI with its 20nm processes and more advanced technologies for making chips, including those designed by Advanced Micro Devices.



Fully-depleted wafers from Soitec, pre-integrate critical characteristics of the transistor within the wafer structure itself. Soitec’s FD wafers offer an early, low-risk migration at the 28nm node down to 10nm and beyond, lowering costs and enabling significant advances in the performance and power efficiency of mobile devices such as smartphones and tablets.

Soitec’s FD-2D product line enables a unique planar approach to fully depleted silicon technology as early as the 28nm node, in which chipmakers can continue to leverage their existing designs and process technologies. FD-2D also enables immediate gains in performance and energy efficiency for mobile and consumer multimedia chips.

The company’s FD-3D product line facilitates the introduction of three-dimensional (FinFET) architectures with reduced time and investment, and drives substantial simplifications in the transistor fabrication process, targeting nodes below 20nm.

Soitec’s proprietary Smart Cut layer transfer technology is said to generate thin layers with high quality and uniformity, bringing the ability to tune starting wafers to successive technology nodes and delivering key advantages as chip manufacturers pursue the best performance, efficiency and manufacturability results.